ADN2817 datasheet(13/35 Pages) AD

13 / 35 page

Preliminary Technical Data

ADN2817/ADN2818

Rev.Pr A | Page 13 of 35

Table 9. Control Register, CTRLB

Config LOL

Reset MISC[4]

System Reset

Reset MISC[2]

0 = LOL pin normal operation

1 = LOL pin is static LOL

Write a 1 followed by

0 to reset MISC[4]

Write a 1 followed by

0 to reset

ADN2817/ADN2818

Set

to 0

Write a 1 followed by

0 to reset MISC[2]

Set

to 0

Set

to 0

Set

to 0

Table 10. Control Register, CTRLC

Signal Degrade Threshold

Signal Degrade Mode

Config LOS

Squelch Mode

0 = Active high LOS

0 = Squelch CLK and

DATA

Set

to 0

Set

to 0

Set

to 0

0=Set SD Threshold to 9mV

1=Set SD Threshold to 1.9x

LOS Threshold

0= Disable Signal Degrade

Mode

1= Enable Signal Degrade

Mode

Set

to 0

1 = Active low LOS

1 = Squelch CLK or

DATA

Table 111. Control Register, CTRLD

CDR Bypass

Disable DATA

Buffer

Disable CLK

Buffer

Initiate PRBS

PRBS Mode

Power Down

0=CDR

Enabled

1=CDR

Disabled

0=Data Buffer

Enabled

1=Data Buffer

Disabled

0=CLK Buffer

Enabled

1=CLK Buffer

Disabled

Set

to 0

Write a 1

followed by 0 to

initiate PRBS

Generate

Sequence

Generate Mode

Detect Mode, compares errors

Detect Mode, O/P to BER only

Detect mode, BER not in use

Table 12. FDDI_MODE

FDDI Enable

Subharmonic Ratio [6..2]

0= FDDI Mode Disabled

1= FDDI Mode Enabled

1 =

= 2

= 3

---------------------

= 31

Set to 0

Table 13. SEL_MODE

Mode Control 2

Mode Control 1

Mode Control 0

Clock Holdover

Mode 2A

Clock Holdover

Mode 2B

Set

to 0

Set

to 0

0=LTD/LTR Mode

1=LTR Mode Only

0= Continuous Rate

1= Single Rate

0= Full Range (12.3M-

2.7G)

1= Limited Range

Set to 1 for Clock

Holdover Mode 2A

Set to 1 for Clock

Holdover Mode 2B

Set

to 0

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