ADN2817 datasheet(11/35 Pages) AD

部件名	ADN2817

功能描述	Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs

PDF	35 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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11 / 35 page

Preliminary Technical Data

ADN2817/ADN2818

Rev.Pr A | Page 11 of 35

I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

000

MSB = 1

SET BY

PIN 19

0 = WR

1 = RD

SLAVE ADDRESS [6...0]

R/W

CTRL.

Figure 7. Slave Address Configuration

SLAVE ADDR, LSB = 0 (WR) A(S)

A(S)

DATA

SUB ADDR

A(S)

DATA

Figure 8. I2C Write Data Transfer

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(M) = LACK OF ACKNOWLEDGE BY MASTER

SLAVE ADDR, LSB = 0 (WR)

SLAVE ADDR, LSB = 1 (RD)

A(S)

SUB ADDR

A(S) DATA A(M)

DATA

A(M)

Figure 9. I2C Read Data Transfer

START BIT

STOP BIT

ACK

SLADDR[4...0]

SLAVE ADDRESS

SUB ADDRESS

DATA

SUB ADDR[6...1]

DATA[6...1]

SCK

SDA

Figure 10. I2C Data Transfer Timing

tBUF

SDA

SCK

tLOW

tHD;STA

tHD;DAT

tSU;DAT

tHIGH

tSU;STA

tSU;STO

tHD;STA

Figure 11. I2C Port Timing Diagram

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