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ADN2817 数据表(PDF) 9 Page - Analog Devices |
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ADN2817 数据表(HTML) 9 Page - Analog Devices |
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9 / 35 page ![]() Preliminary Technical Data ADN2817/ADN2818 Rev.Pr A | Page 9 of 35 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC VEE LOS SDA SCK SADDR5 VCC VEE AU T OM OD E VCC VREF NIN PIN SL ICEP SL I CEN VEE 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 AD N 2817 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 AUTOMODE DI Set to Logic Low to enable analog voltage output mode for BER monitor 2 VCC P Power for Limamp, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 SLICEP AI Differential Slice Level Adjust Input. 7 SLICEN AI Differential Slice Level Adjust Input. 8 VEE P GND for Limamp, LOS. 9 THRADJ AI LOS Threshold Setting Resistor. 10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz. 11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz. 12 VCC P VCO Power. 13 VEE P VCO GND. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss of Lock Indicator. LVTTL active high. 17 VEE P FLL Detector GND. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 20 SCK DI I2C Clock Input. 21 SDA DI I2C Data Input. 22 LOS DO Loss of Signal Detect Output. Active high. LVTTL. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. CML. 26 CLKOUTP DO Differential Recovered Clock Output. CML. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL. 28 DATAOUTN DO Differential Recovered Data Output. CML. 29 DATAOUTP DO Differential Recovered Data Output. CML. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 32 VBER AO Relative BER monitor output. Referred to GND, Analog Voltage Output. Exposed Pad Pad P Connect to GND 1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. |
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