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4LS 数据表(PDF) 60 Page - ams AG |
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4LS 数据表(HTML) 60 Page - ams AG |
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60 / 115 page  Document Feedback 4LS Digital Interface Datasheet • PUBLIC DS000542 • v3-01 • 2022-Nov-17 114 │ 59 Parameter Description Min Maximum Unit VOH High Level Output Voltage VDDIO – 0.6 VDDIO + 0.6 V Figure 88: AC Electrical Conditions Parameter Description Min Maximum Unit FSCLK SCLK Frequency. < 1/4 of MCLK up to 12.5 MHz V TLS1 Time from falling edge of N_CS to first rising edge of SCLK. 50 ns TLS2 Time form last falling edge of SCLK to the rising edge of N_CS. 50 ns TSET Time between MOSI stable and rising edge of SCLK. 10 ns TLH Time between SPI cycles (between rising and falling edge of N_CS); minimum SPI idle time. 1 ns THold Time that MOSI need to be stable after the rising edge of SCLK. 5 ns TDelay Time between falling edge of SCLK and stable data on MISO. 10 ns TRise Rise time for SPI signals. 2 20 ns TFall Fall time for SPI signals. 2 20 ns Figure 89: Time Guard Between Signals |
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