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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 39

7.11

Timings / State Machine

7.11.1

Pixel Timing Diagram Considerations

●

When stated a value in time (usually ns or µs), this is a fixed or minimum value.

●

When stated a time duration in 'X' times TMCLK, this is number of clocks that must be respected,

independently of the clock frequency. A clock is equal to TMCLK.

●

START_AD signal can only be sent to the sensor, after the falling edge from the last sent

SAMPLE signal. It is recommend a minimum number of clocks between SAMPLE falling edge

and START_AD rising edge.

●

8 x TMCLK for 12-bit mode at 60 MHz

●

12 x TMCLK for 8-bit mode at 80 MHz

●

The SAMPLE signal rising edge from the current exposure, can only be sent after A/D

conversion period of the previous exposure.

●

START READOUT must always be sent before the next A/D conversion (START_AD pulse

rising edge).

●

For the correct operation of the sensor, the minimum time in TMCLK for START_READOUT pulse

is presented in Figure 56.

Figure 56:

START_READOUT Pulse Configuration

Frequency

Auto Start Readout(1)

External Start Readout

Frequency less or equal

to 80 MHz

Can use Auto Start Readout

Minimum 20 x TMCLK for 4LS15K

Minimum 12 x TMCLK for 4LS10K

Minimum 8 x TMCLK for 4LS5K

(1)

Can be used, however it is recommended to set the readout using an external pulse, as in Figure 56.

Figure 57:

Timing Diagram Assuming Default Configuration for Standard Mode

Exposure On

Act ive

RST_CVC

RST_CDS

SAMPLE

EXPOSURE

START_AD

ADC

START_READOUT

READOUT

LVAL

DATA

Act ive

Train in g Sequence

Data

(A)

(B)

(D)

(I)

(E)

(F)

(I)

Act ive

(C)

(G)

(H)

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