4LS datasheet(77/115 Pages) AMSCO

77 / 115 page

Document Feedback

4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 76

9.1.31

Status 5 Register (Address 0x1E)

Figure 129:

STS5Reg

Address: 0x1E

Default Value: 0x30

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:7

VREF CDS Buff Half

Current

When set to ‘1’ reduces the VREF CDS

buffer current to half.

6:6

VRST Pixel Buff Half

Current

When set to ‘1’ reduces the VRST pixel

buffer current to half.

5:4

CLK Phase

11b

It is used to choose between Rise-

Edge and Fall-Edge of MLCK to

perform the serializer synchronization.

3:2

PLL Resistor

00b

Increases the PLL resistor for

stabilization purposes.

1:0

PLL Charge Pump

00b

To be used to configure the current on

the PLL charge pump.

Figure 130:

Effect on MLCK Provided to Serializer of 4LS

CLK Phase

Bit 5

Bit 4

Effect on MLCK Provided to Serializer

Copy of MCLK

Inverted copy of MCLK

Copy of MCLK delayed by 1 PLL clock

Copy of MCLK delayed by 2 PLL clocks

Figure 131:

PLL Charge Pump Programmed by Register

Bit 1

Bit 0

Current [µA]

1.6

3.2

4.9

6.5

4LS 数据表(PDF) 77 Page - ams AG

4LS 数据表(HTML) 77 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载