AD9923ABBCZ datasheet(6/88 Pages) AD

6 / 88 page

AD9923A

Rev. 0 | Page 6 of 88

Parameter

Conditions/Comments

Min

Typ

Max

Unit

BLACK LEVEL CLAMP

Measured at ADC output

Clamp Level Resolution

1024

Steps

Minimum Clamp Level (Code 0)

LSB

Maximum Clamp Level (Code 1023)

255

LSB

ANALOG-TO-DIGITAL CONVERTER (ADC)

Resolution

Bits

Differential Nonlinearity (DNL)

−1.0

±0.5

+1.0

LSB

No Missing Codes

Guaranteed

Full-Scale Input Voltage

2.0

VOLTAGE REFERENCE

Reference Top Voltage (REFT)

2.0

Reference Bottom Voltage (REFB)

1.0

SYSTEM PERFORMANCE

Includes entire signal chain

Gain Accuracy

Low Gain (VGA Code 15)

Default CDS gain (0 dB)

6.0

6.5

7.0

Maximum Gain (VGA Code 1023)

42.0

42.5

43.0

Peak Nonlinearity, 500 mV Input Signal

12 dB gain applied

0.1

Total Output Noise

AC-grounded input, 6 dB gain applied

1.0

LSB rms

Power Supply Rejection (PSR)

Measured with step change on supply

1 Input signal characteristics are defined as shown in Figure 3.

200mV MAX

OPTICAL BLACK PIXEL

500mV TYP

RESET TRANSIENT

1V MAX

INPUT SIGNAL RANGE

(0dB CDS GAIN)

Figure 3. Signal Characteristics

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.

Table 6.

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

MASTER CLOCK, CLI

CLI Clock Period

tCONV

27.8

CLI High/Low Pulse Width

11.2

13.9

16.6

Delay from CLI Rising Edge to Internal Pixel Position 0

tCLIDLY

AFE CLPOB Pulse Width1, 2

Pixels

Allowable Region for HD Falling Edge to CLI Rising Edge

Only valid in slave mode

tHDCLI

tCONV − 2

SHP Inhibit Region

Only valid in slave mode

tSHPINH

Edge location

AFE SAMPLE LOCATION1

SHP Sample Edge to SHD Sample Edge

tS1

11.6

13.9

DATA OUTPUTS

Output Delay from DCLK Rising Edge1

tOD

Inhibited Area for DOUTPHASE Edge Location

SHD

SHD + 11

Edge location

Pipeline Delay from SHP/SHD Sampling to Data Output

Cycles

SERIAL INTERFACE

Maximum SCK Frequency

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

SCK Falling Edge to SDATA Valid Read

tDV

1 Parameter is programmable.

2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

AD9923ABBCZ 数据表(PDF) 6 Page - Analog Devices

AD9923ABBCZ 数据表(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载