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AD9923ABBCZ 数据表(PDF) 65 Page - Analog Devices

部件名 AD9923ABBCZ
功能描述  CCD Signal Processor with V-Driver and Precision Timing??Generator
PDF  88 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9923ABBCZ 数据表(HTML) 65 Page - Analog Devices

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AD9923A
Rev. 0 | Page 65 of 88
3
15
6
12
0.1µF
4.7µF
6.3V
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
10V
0.1µF
25V
0.1µF
0.1µF
4.7µF
10V
4.7µF
6.3V
2.2µF
25V
SERIAL INTERFACE (FROM ASIC/DSP)
VERTICAL SYNC (TO/FROM ASIC/DSP)
HORIZONTAL SYNC (TO/FROM ASIC/DSP)
RESETB (FROM ASIC/DSP)
+3V SUPPLY
+3V SUPPLY
+3V SUPPLY
+3V SUPPLY
MASTER CLOCK INPUT
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
VSUB OUTPUT (TO CCD BIAS CIRCUIT)
STROBE CONTROL OUTPUT
MECHANICAL SHUTTER CONTROL OUTPUT
CCDGND
H, RG OUTPUTS
(TO CCD)
+3V ANALOG
SUPPLY
+3V H,
RG SUPPLY
+3V H,
RG SUPPLY
VERTICAL OUTPUTS (TO CCD)
SUBCK OUTPUT (TO CCD)
NC = NOT INTERNALLY
CONNECTED
DCLK OUTPUT
DATA OUTPUTS
REFB
REFT
CCDIN
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
RG
HL
H4
H3
H2
H1
CCD SIGNAL INPUT
RGVSS
HVSS
AVDD
TCVDD
RGVDD
HVDD
AD9923ABBCZ
(Not to Scale)
VH SUPPLY
VL SUPPLY
DRVDD
DVDD1
DVDD2
DVDD2
DVDD2
TEST3
VDR_EN
NC
TEST1
TEST0
DRVSS
DVSS1
DVSS2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L4
E1
K8
L8
L7
J8
K11
K4
J7
J5
L5
F2
K9
A11
E6
G2
G3
H9
J6
J9
J10
J11
K7
L1
L6
L9
L11
A2
A3
A5
A6
C10
B11
C11
D11
E11
F11
A1
B2
B3
B4
B5
A4
B6
B7
B9
A10
D10
A7
B8
B10
D9
TCVSS
V-DRIVER ENABLE
(FROM ASIC/DSP)
Figure 83. Typical Circuit Configuration When Using Software Sync Function



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