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MASTERGAN1 数据表(PDF) 6 Page - STMicroelectronics |
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MASTERGAN1 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 27 page ![]() 3.2 Recommended operating conditions Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified) Symbol Parameter Note Min Max Unit VS High voltage bus 0 520 V VCC Supply voltage 4.75 9.5 V PVCC-PGND PVCC to PGND low side supply(1) 4.75 6.5 V Best performance 5 6.5 V PVCC Low-side driver supply 3 8.5 V VCC-PVCC VCC to PVCC pin voltage -3 3 V PGND Low-side driver ground(1) -2 2 V DT Suggested minimum deadtime 5 ns TIN_MIN Minimum duration of input pulse to obtain undistorted output pulse 120 ns VBO BOOT to OUTb pin voltage(2) 4.4 6.5 V Best performance 5 6.5 V BOOT BOOT to GND voltage 0(3) 530 V Vi Logic inputs voltage range 0 20 V TJ Junction temperature -40 125 °C 1. PGND internally connected to SENSE. 2. OUTb internally connected to OUT. 3. 5 V is recommended during high-hide turn-on. 3.3 Thermal data Table 4. Thermal data Symbol Parameter Value Unit Rth(J-CB) Thermal resistance junction to each GaN transistor exposed pad, typical 1.9 °C/W Rth(J-A) Thermal resistance junction-to-ambient(1) 17.5 °C/W 1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors. MASTERGAN1 Recommended operating conditions DS13417 - Rev 3 page 6/27 |
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