6.5

Thermal shutdown

The integrated gate driver has a thermal shutdown protection.

When junction temperature reaches the TTSD temperature threshold, the device turns off both GaN transistors

leaving the half-bridge in 3-state and signaling the state forcing SD/OD pin low. SD/OD pin is released when

junction temperature is below TTSD-THYS and SD/OD is below VTSD.

GaN are driven again according to inputs when SD/OD rises above Vih.

The thermal smart shutdown system gives the possibility to increase the time constant of the external RC network

(that determines the disable time after the overtemperature event) up to very large values without delaying the

protection.

Figure 18. Thermal shutdown timing waveform

THERMAL SHUTDOWN CIRCUIT

GH/GL

OD gate

(internal)

Fast shut down

the driver outputs are switched off

disable time

SD/OD

TTSD

THYS

TTSD -

Vih

V

0 V

TSD

VOD

TJ

t1

t2

VPU

SD/OD

FROM / TO

CONTROLLER

COD

THERMAL

SHUTDOWN

LOGIC

RON_OD

RPD_SD

ROD_ext

2

1

immediately after overtemperature

MASTERGAN1

Thermal shutdown

DS13417 - Rev 3

page 17/27