CC2550-RTY1 datasheet(15/55 Pages) TI

15 / 55 page

CC2550

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 15 of 54

10.1

Chip Status Byte

When the header byte, data byte or command

strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2550 on the SO

pin. The status byte contains key status

signals, useful for the MCU. The first bit, s7, is

the CHIP_RDYn signal; this signal must go low

before the first positive edge of SCLK. The

CHIP_RDYn

signal indicates that the crystal is

running and the regulated digital supply

voltage is stable.

Bits 6, 5 and 4 comprise the STATE value. This

value reflects the state of the chip. The XOSC

and power to the digital core is on in the IDLE

state, but all other modules are in power down.

The frequency and channel configuration

should only be updated when the chip is in this

state. The TX state will be active when the

chip is transmitting.

The last four bits (3:0) in the status byte con-

tains FIFO_BYTES_AVAILABLE. This field

contains the number of bytes free for writing

into

the

FIFO.

When

FIFO_BYTES_AVAILABLE=15

, 15 or more

bytes are free.

Table 15 gives a status byte summary.

Bits

Name

Description

CHIP_RDYn

Stays high until power and crystal have stabilized. Should always be low when using

the SPI interface.

6:4

STATE[2:0]

Indicates the current main state machine mode

Value

State

Description

000

Idle

IDLE state

(Also reported for some transitional states instead

of SETTLING or CALIBRATE)

001

Not used

(RX)

Not used, included for software compatibility

with

CC2500 transceiver

010

Transmit mode

011

FSTXON

Fast TX ready

100

CALIBRATE

Frequency synthesizer calibration is running

101

SETTLING

PLL is settling

110

Not used

(RXFIFO_OVERFLOW)

Not used, included for software compatibility

with

CC2500 transceiver

111

TXFIFO_UNDERFLOW

TX FIFO has underflowed. Acknowledge with

SFTX

3:0

FIFO_BYTES_AVAILABLE[3:0]

The number of free bytes in the TX FIFO. If FIFO_BYTES_AVAILABLE=15, it

indicates that 15 or more bytes are free.

Table 15: Status byte summary

10.2

Registers Access

The configuration registers on the

CC2550 are

located on SPI addresses from 0x00 to 0x2F.

Table 24 on page 36 lists all configuration

registers. The detailed description of each

page 38. All configuration registers can be

both written and read. The read/write bit

controls if the register should be written or

read. When writing to registers, the status byte

is sent on the SO pin each time a header byte

or data byte is transmitted on the SI pin.

When reading from registers, the status byte is

sent on the SO pin each time a header byte is

transmitted on the SI pin.

Registers with consecutive addresses can be

accessed in an efficient way by setting the

burst bit in the address header. The address

sets the start address in an internal address

counter. This counter is incremented by one

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