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AT83C5136-RDTUL 数据表(PDF) 93 Page - ATMEL Corporation |
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AT83C5136-RDTUL 数据表(HTML) 93 Page - ATMEL Corporation |
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93 / 171 page ![]() 93 AT83C5134/35/36 7683B–USB–03/07 Figure 45. Format and State in the Master Receiver Mode S SLA R A Data 08h 40h 58h S SLA R A P W MT 10h 48h A or A continues 38h 38h A continues 68h Other master Other master 78h B0h To corresponding states in slave mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost and addressed as slave A continues Other master n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus A Data P A 50h MR Arbitration lost in slave address or acknowledge bit Data A |
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