AT83C5136-RDTUL datasheet(15/171 Pages) ATMEL

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AT83C5134/35/36

7683B–USB–03/07

Figure 9. Crystal Connection

PLL

PLL Description

The AT83C5134/35/36 PLL is used to generate internal high frequency clock (the USB

Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL

clock is used to generate the USB interface clock. Figure 10 shows the internal structure

of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block

makes the comparison between the reference clock coming from the N divider and the

reverse clock coming from the R divider and generates some pulses on the Up or Down

signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON

in PLLCON register (see Figure 10) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by

injecting or extracting charges from the external filter connected on PLLF pin (see

Figure 11). Value of the filter components are detailed in the Section “DC

Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF pro-

duced by the charge pump. It generates a square wave signal: the PLL clock.

Figure 10. PLL Block Diagram and Symbol

Figure 11. PLL Filter Connection

The typical values are: R = 560 Ω, C1 = 820 pf, C2 = 150 pF.

VSS

PLLEN

PLLCON.1

N3:0

N divider

R divider

VCO

USB Clock

USBclk

OSC

clk

(

)

-----------------------------------------------

OSC

CLOCK

PFLD

PLOCK

PLLCON.0

PLLF

CHP

Vref

Down

R3:0

USB

CLOCK

USB Clock Symbol

VSS

PLLF

VSS

AT83C5136-RDTUL 数据表(PDF) 15 Page - ATMEL Corporation

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