AT83C5136-RDTUL datasheet(18/171 Pages) ATMEL

18 / 171 page

AT83C5134/35/36

7683B–USB–03/07

Table 15. CKCON1 (S:AFh)

Clock Control Register 1

Reset Value = 0000 0000b

Table 16. PLLCON (S:A3h)

PLL Control Register

Reset Value = 0000 0000b

Table 17. PLLDIV (S:A4h)

PLL Divider Register

Reset Value = 0000 0000

SPIX2

Bit Number

Bit

Mnemonic Description

7-1

Reserved

The value read from this bit is always 0. Do not set this bit.

SPIX2

SPI Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

EXT48

PLLEN

PLOCK

Bit Number

Bit

Mnemonic Description

7-3

Reserved

The value read from this bit is always 0. Do not set this bit.

EXT48

External 48 MHz Enable Bit

Set this bit to bypass the PLL and disable the crystal oscillator.

Clear this bit to select the PLL output as USB clock and to enable the crystal

oscillator.

PLLEN

PLL Enable Bit

Set to enable the PLL.

Clear to disable the PLL.

PLOCK

PLL Lock Indicator

Set by hardware when PLL is locked.

Clear by hardware when PLL is unlocked.

Bit Number

Bit

Mnemonic Description

7-4

R3:0

PLL R Divider Bits

3-0

N3:0

PLL N Divider Bits

AT83C5136-RDTUL 数据表(PDF) 18 Page - ATMEL Corporation

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