AT83C5136-RDTUL datasheet(32/171 Pages) ATMEL

32 / 171 page

AT83C5134/35/36

7683B–USB–03/07

When an instruction accesses an internal location above address 7Fh, the CPU knows

whether the access is to the upper 128 bytes of data RAM or to SFR space by the

addressing mode used in the instruction.

•

Instructions that use direct addressing access SFR space. For example: MOV

0A0H, # data, accesses the SFR at location 0A0h (which is P2).

•

Instructions that use indirect addressing access the Upper 128 bytes of data RAM.

For example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at

address 0A0h, rather than P2 (whose address is 0A0h).

•

The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared

and MOVX instructions. This part of memory which is physically located on-chip,

logically occupies the first bytes of external data memory. The bits XRS0 and XRS1

are used to hide a part of the available ERAM as explained in Table 35. This can be

useful if external peripherals are mapped at addresses already used by the internal

ERAM.

•

With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An

access to ERAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For

example, with EXTRAM = 0, MOVX atR0, # data where R0 contains 0A0H,

accesses the ERAM at address 0A0H rather than external memory. An access to

external data memory locations higher than the accessible size of the ERAM will be

performed with the MOVX DPTR instructions in the same way as in the standard

80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and

read timing signals. Accesses to ERAM above 0FFH can only be done by the use of

DPTR.

•

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard

80C51. MOVX at Ri will provide an eight-bit address multiplexed with data on Port0

and any output port pins can be used to output higher order address bits. This is to

provide the external paging capability. MOVX @DPTR will generate a sixteen-bit

address. Port2 outputs the high-order eight address bits (the contents of DPH) while

Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX at Ri and

MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7

(RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and

upper RAM) internal data memory. The stack may not be located in the ERAM.

The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses

are extended from 6 to 30 clock periods. This is useful to access external slow

peripherals.

AT83C5136-RDTUL 数据表(PDF) 32 Page - ATMEL Corporation

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