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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AT83C5136-RDTUL 数据表(PDF) 102 Page - ATMEL Corporation |
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AT83C5136-RDTUL 数据表(HTML) 102 Page - ATMEL Corporation |
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102 / 171 page  102 AT83C5134/35/36 7683B–USB–03/07 USB Controller . Description The USB device controller provides the hardware that the AT89C5131 needs to inter- face a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of the AT89C5131 PLL (see Section “PLL”, page 15) divided by a clock prescaler. This clock is used to generate a 12 MHz Full-speed bit clock from the received USB differen- tial data and to transmit data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus. The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff- ing, CRC generation and checking, and the serial-parallel data conversion. The Universal Function Interface (UFI) realizes the interface between the data flow and the Dual Port RAM. Figure 48. USB Device Controller Block Diagram SIE DPLL USB D+/D- Buffer UFI 12 MHz 48 MHz +/- 0.25% D+ Up to 48 MHz UC_sysclk C51 Microcontroller Interface D- |
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