AT83C5136-RDTUL datasheet(138/171 Pages) ATMEL

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138

AT83C5134/35/36

7683B–USB–03/07

Power Management

Idle Mode

An instruction that sets PCON.0 indicates that it is the last instruction to be executed

before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to

the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is

preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word,

Accumulator and all other registers maintain their data during Idle. The port pins hold

the logical states they had at the time Idle was activated. ALE and PSEN hold at logic

high level.

There are two ways to terminate the Idle mode. Activation of any enabled interrupt will

cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will

be serviced, and following RETI the next instruction to be executed will be the one fol-

lowing the instruction that put the device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-

ing normal operation or during an Idle. For example, an instruction that activates Idle

can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt

service routine can examine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock

oscillator is still running, the hardware reset needs to be held active for only two

machine cycles (24 oscillator periods) to complete the reset.

Power-down Mode

To save maximum power, a power-down mode can be invoked by software (refer to

Table 13, PCON register).

In power-down mode, the oscillator is stopped and the instruction that invoked power-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the power-down mode is terminated. VCC can be lowered to save further

power. Either a hardware reset or an external interrupt can cause an exit from power-

down. To properly terminate power-down, the reset or external interrupt should not be

executed before VCC is restored to its normal operating level and must be held active

long enough for the oscillator to restart and stabilize.

Only:

•

external interrupt INT0,

•

external interrupt INT1,

•

Keyboard interrupt and

•

USB Interrupt

are useful to exit from power-down. For that, interrupt must be enabled and configured

as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power

down mode, 1024 clocks are necessary to exit to power-down mode and enter in oper-

ating mode.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as

detailed in Figure 69. When both interrupts are enabled, the oscillator restarts as soon

as one of the two inputs is held low and power-down exit will be completed when the first

input is released. In this case, the higher priority interrupt service routine is executed.

Once the interrupt is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put AT83C5134/35/36 into power-down mode.

AT83C5136-RDTUL 数据表(PDF) 138 Page - ATMEL Corporation

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