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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AT83C5136-RDTUL 数据表(PDF) 153 Page - ATMEL Corporation |
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AT83C5136-RDTUL 数据表(HTML) 153 Page - ATMEL Corporation |
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153 / 171 page  153 AT83C5134/35/36 7683B–USB–03/07 External Data Memory Read Cycle Serial Port Timing - Shift Register Mode Table 111. Symbol Description (F = 40 MHz) Table 112. AC Parameters for a Fix Clock (F = 40 MHz) Table 113. AC Parameters for a Variable Clock ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 T AVWL TLLWL T RLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ T WHLH T RLRH T LLDV T RHDX T LLAX TAVDV Symbol Parameter T XLXL Serial port clock cycle time T QVHX Output data set-up to clock rising edge T XHQX Output data hold after clock rising edge T XHDX Input data hold after clock rising edge T XHDV Clock rising edge to input data valid Symbol Min Max Units TXLXL 300 ns TQVHX 200 ns T XHQX 30 ns T XHDX 0 ns T XHDV 117 ns Symbol Type Standard Clock X2 Clock X Parameter for -M Range Units T XLXL Min 12 T 6 T ns T QVHX Min 10 T - x 5 T - x 50 ns T XHQX Min 2 T - x T - x 20 ns T XHDX Min x x 0 ns T XHDV Max 10 T - x 5 T- x 133 ns |
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