IA88C00-PDW48C-R datasheet(27/80 Pages) INNOVASIC

27 / 80 page

IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG 21 0 050519-00

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Page 27 of 80

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Figure 21. Counter 0 Mode, R224

Bit

Initial Value

Read/Write

R/W

D0 - When this bit is set to 1, the counter/timer is enabled. Operation begins on the rising edge of the first

processor clock period following the setting of this bit from a previously cleared value. Writing a 1 in this

field when the previous value was 1 has no effect on the operation of the counter/timer. When this bit is

cleared to 0, the counter/timer performs no operation during the next (and subsequent) processor clock

periods. A hardware reset forces this bit to 0.

Both counters are clocked by the rising edge of the incoming signal on P26 or p36 after the counter is

enabled. The maximum frequency of the external clock signal applied to P36 (or P26) equals the

maximum Xtal frequency divided by 4. The maximum gauaranteed Xtal frequency is 20 MHz, which

implies a maximum counter frequency of 5 MHz.

D1 - Reset/End of Count Status - This bit is set to 1 each time the counter reaches 0. Writing a 1 to this

bit resets it, while writing a 0 has no effect.

D2 - Zero Count Interrupt Enable - When this bit is set to 1, the counter/timer generates an interrupt

request when it counts to 0. A hardware reset forces this bit to 0.

D3 - Software Capture - When this bit is set to 1, the current counter value is loaded into the capture

D4 - Software Trigger - This bit is effectively "ORed" with the external rising-edge trigger input and can

be used by the software to force a trigger signal. This bit produces a trigger signal regardless of the setting

of the Input Pin Assignment field of the Mode register. This bit is automatically cleared following the

trigger.

D5 - Load Counter - The contents of the Time Constant register are transferred to the Counter prescaler

one clock period after this bit is set. This operation alone does not start the counter. This bit is

automatically cleared following the load.

D6 - Count Up/Down - This bit determines the count direction if internal up/down control is specified in

the Mode register. 1 indicates up; 0 indicates down.

D7 - Continuous/Single Cycle - When this bit is set to 1, the counter is reloaded with the time-constant

value when the counter reaches the end of the terminal count. The terminal count for down counting is

0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.

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