IA88C00-PDW48C-R datasheet(33/80 Pages) INNOVASIC

33 / 80 page

IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG 21 0 050519-00

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D4 - WUEB - Wake-up Enable - If this bit is set to 1, wake-up mode is enabled for both the transmitter

and the receiver. The transmitter adds a bit beyond those specified by the bits/character and the parity.

This added bit has the value specified in the Transmit Wake-up Value (TWUVAL) in the UMA register

(ControlRegR250B0). The reveiver expects a Wake-Up bit value in the incoming data stream after the

parity bit and compares this value with that specified in the Received Wake-Up value (RWVAL) bit in the

UMA register. The resulting action depends on the configuration of the Wake-up feature.

D5 - STPBTS - Stop Bits - This bit determines the number of stop bits added to each character

transmitted from the UART transmit section. If this bit is a 0, one stop bit is added. If this bit is a 1, two

stop bits are added. The receiver always checks for at least one stop bit. A hardware reset forces this bit to

D6 - SENBRK - Send Break - When set to 1, this bit forces the transmit section to continuously output

0s, beginning with the following transmit clock, regardless of any data being transmitted at the time. This

bit functions whether or not the transmitter is enabled. When this bit is cleared to 0, the transmit section

continues to send the contents of the Transmit Data Register. A hardware reset forces this bit to 0.

D7 - TXDTSEL - Transmit Data Select - This bit has an effect only if port pin P31 is configured as an

output. If this bit is set to 1, the serial data coming out of the transmit section is reflected on the P31 pin.

If this bit is set to 0, P31 acts as a normal port and P31 data is reflected on the P31 pin. A hardware reset

forces this bit to 0.

Figure 30. UART Receive Control (URC), R236 Bank 0

Bit

Initial Value

Read/Write

R/W

D0 - RCA - Receive Character Available - This is a status bit that is set to a 1 when data is available in

the receive buffer (UIOR). When the CPU reads the receive buffer, it automatically clears this bit to 0. A

write to this possition has not effect. A hardware reset forces this bit to 0.

D1 - RENB - Receive Enable - When this bit is set to 1, the receive operation begins. This bit should be

set only after all other receive parameters are established and the reciver is completely initialized. A

hardware reset clears this bit to 0.

D2 - PERR - Parity Error - This is a status bit. When parity is enabled, this bit is set to 1 and buffered

with the character whose parity does not match the programmed parity (even/odd). This bit is latched so

that once an error occurs, it remains set until it is cleared to 0 by writing a 1 to this bit position.

D3 - OVERR - Overrun Error - This status bit indicates that the receive buffer has not been read and

another character has been received. Only the character that has been written over is flagged with this

error. Once set, this bit remains set until cleared to 0 by writing a 1 to this bit position.

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