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IA88C00-PDW48C-R 数据表(PDF) 30 Page - InnovASIC, Inc

部件名 IA88C00-PDW48C-R
功能描述  Microcontroller
PDF  80 Pages
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制造商  INNOVASIC [InnovASIC, Inc]
网页  http://www.innovasic.com
标志 INNOVASIC - InnovASIC, Inc

IA88C00-PDW48C-R 数据表(HTML) 30 Page - InnovASIC, Inc

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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright © 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 30 of 80
1.888.824.4184
Figure 26. Counter 1 Capture Register (Low Byte) (C1CL), R229 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
C1C7 – C1C0
Initial Value
X
X
X
X
X
X
X
X
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This 16-bit register pair is used to hold the counter value saved when using the "capture on external
event" function. This register will capture at the rising edge of the I/O pin or when software capture is
asserted. When the bi-value mode of operation is enabled, this register is used as a second Time Constant
register and the counter is alternately loaded from each.
Figure 27a. Counter 0 Prescaler (CTPRS), R230 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
CT1
Not Used
CT0
Initial Value
0
0
1
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register controls the source of the timer signal when in internal mode. An 8-bit prescaler for each
counter is implemented. The control bit operate as follows:
CT0/CT1
Prescale
000
XTAL/2
001
010
011
100
XTAL/4
XTAL/8
XTAL/16
XTAL/32
101
XTAL/64
110
XTAL/128
111
XTAL/256
Only the prescaler of CT1 is activated when the counters are cascaded.



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