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IA88C00-PDW48C-R 数据表(PDF) 44 Page - InnovASIC, Inc

部件名 IA88C00-PDW48C-R
功能描述  Microcontroller
PDF  80 Pages
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制造商  INNOVASIC [InnovASIC, Inc]
网页  http://www.innovasic.com
标志 INNOVASIC - InnovASIC, Inc

IA88C00-PDW48C-R 数据表(HTML) 44 Page - InnovASIC, Inc

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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright © 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 44 of 80
1.888.824.4184
Figure 47. External Memory Timing Register, R254 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
1
0
0
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register controls all the extended bus timing features.
D0 - DMA Select - If 0, DMA uses register file space. If 1, it uses Data Memory.
D1 - Stack Select - If 0, stack is located in register file space. If 1, it is located in Data Memory.
Figure 48. Interrupt Priority Register (IPR), R255 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
X
X
X
X
X
X
X
X
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The Interrupt Priority register defines the priority order of the interrupt levels. Interrupts should be
globally disabled before writing to this register.
D0 - Group A - 0=IRQ0 > IRQ1; 1=IRQ1 > IRQ0.
D2 - Group B - 0=IRQ2>(IRQ3,IRQ4); 1=(IRQ3,IRQ4) > IRQ2.
D3 - Subgroup B - 0=IRQ3>IRQ4; 1=IRQ4>IRQ3.
D5 - Group C - 0=IRQ5>(IRQ6,IRQ7); 1=(IRQ6,IRQ7)>IRQ5.
D6 - Subgroup C - 0=IRQ6>IRQ7; 1=IRQ7>IRQ6.



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