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IA88C00-PDW48C-R 数据表(PDF) 67 Page - InnovASIC, Inc |
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IA88C00-PDW48C-R 数据表(HTML) 67 Page - InnovASIC, Inc |
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67 / 80 page ![]() IA88C00 Data Sheet Microcontroller As of Production Version -01 Copyright © 2005 ENG21 1 030617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 67 of 80 1.888.824.4184 DC Characteristics Symbol Parameter Min Max Unit Condition VCH Clock Input High Voltage 3.5 VCC V Driven by External Clock Generator VCL Clock Input Low Voltage -0.3 1.5 V Driven by External Clock Generator VIH Input High Voltage 2.2 VCC V VIL Input Low Voltage -0.3 0.8 V VRH Reset Input High Voltage 3.8 VCC V VRL Reset Input Low Voltage -0.3 0.8 V VOH Output High Voltage 3.5 V IOH = -400 µA VOL Output Low Voltage 0.4 V IOL = +400 mA VIL Input Leakage -10 10 µA IOL Output Leakage -10 10 µA IIR Reset Input Current -50 µA ICC VCC Supply Current 90 mA [1] ICC1 Standby Current 5 mA @ 20 MHz [2] 10 mA @ 30 MHz [2] ICC2 Standby Current 20 µA [3] NOTES Following are estimated values: 1. In this case all outputs and I/O pins are floating. 2. Estimated Values, not tested. HALT mode is invoked with UART CT0 and CT1 deactivated with all input pins tied to VCC or VSS. 3. Estimated Values, not tested. STOP mode is invoked with all input pins tied to VCC or VSS. |
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