IA88C00-PDW48C-R datasheet(31/80 Pages) INNOVASIC

31 / 80 page

IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG 21 0 050519-00

www.Innovasic

Innovasic.com

Innovasic Semiconductor

Page 31 of 80

1.888.824.4184

Figure 28b. Watch Dog Timer and Stop Mode Recovery Register (WDT/SMR) R230 Bank0

Bit

WDT time-out

WDT

Enable

WDT in

Stop

WDT

Source

SMR

SMR Source

Initial Value

Read/Write

R/W

This register controls the Watchdog Timer time-out and Stop recovery mode.

D1, D0 Stop Mode Recovery source select.

Bit D0 and D1 determine the Stop Mode Recovery source.

Recovery from RESET only

Recovery from P22 and RESET

Recovery from P32 and RESET

Recovery from any input for Port 4 and RESET

A hardware reset forces D0 and D1 to zero.

D2 Stop Recovery Edge

A 1 in this position indicates that a rising edge on any one of the recovery sources wakes the IA88C00

from Stop mode. A 0 indicates falling edge recovery. The reset value is 0.

D3 XTAL1/RC Select for WDT

When a zero is written to D3, the clock of the WDT is driven by the on-board RC oscillator. If D3 is set to

1, the WDT is driven by XTAL1. D3 has a zero reset value.

D4 WDT Enable During STOP or HALT

When this bit is set, WDT is enabled during STOP or HALT. In this case, recovery from STOP or HALT

should be performed before the selected time-out. A 0 in this bit location disables the WDT while the

IA88C00 is stopped or halted. A hardware reset forces this bit to a zero.

IA88C00-PDW48C-R 数据表(PDF) 31 Page - InnovASIC, Inc

IA88C00-PDW48C-R 数据表(HTML) 31 Page - InnovASIC, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载