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IA88C00-PDW48C-R 数据表(PDF) 29 Page - InnovASIC, Inc

部件名 IA88C00-PDW48C-R
功能描述  Microcontroller
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INNOVASIC [InnovASIC, Inc]
网页  http://www.innovasic.com
标志 INNOVASIC - InnovASIC, Inc

IA88C00-PDW48C-R 数据表(HTML) 29 Page - InnovASIC, Inc

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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright © 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 29 of 80
1.888.824.4184
Figure 23. Counter 0 Capture Register (High Byte) (C0CH), R226 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
X
X
X
X
X
X
X
X
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This 16-bit register pair is used to hold the counter value saved when using the "capture on external
event" function. This register will capture at the rising edge of the I/O pin or when software capture is
asserted. When the bi-value mode of operation is enabled, this register is used as a second Time Constant
register and the counter is alternately loaded from each.
Figure 24. Counter 0 Capture Register (Low Byte) (C0CL), R227 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
X
X
X
X
X
X
X
X
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This 16-bit register pair is used to hold the counter value saved when using the "capture on external
event" function. This register will capture at the rising edge of the I/O pin or when software capture is
asserted. When the bi-value mode of operation is enabled, this register is used as a second Time Constant
register and the counter is alternately loaded from each.
Figure 25. Counter 1 Time Constant Register (High Byte) (C1CTH), R228 Bank 1
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
X
X
X
X
X
X
X
X
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This 16-bit register pair holds the value that is automatically loaded into the counter/timer (1) when the
counter/timer is enabled, (2) when the count reaches zero in continuous mode or (3) when the trigger is
asserted in re-trigger mode. If capture on both edges is enabled, this register captures the contents of the
counter on the falling edge of the I/O pin.



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