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IA88C00-PDW48C-R 数据表(PDF) 37 Page - InnovASIC, Inc |
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IA88C00-PDW48C-R 数据表(HTML) 37 Page - InnovASIC, Inc |
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37 / 80 page ![]() IA88C00 Data Sheet Microcontroller As of Production Version -01 Copyright © 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 37 of 80 1.888.824.4184 Figure 34. Port 0 Mode Control Register (P0M), R240 Bank 0 Bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Initial Value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The Port 0 Mode register programs each bit of Port 0 as an address output (part of an external memory interface) or as an I/O bit. When a bit of this register is 1, the corresponding bit of Port 0 is defined as an address output. When 0, the corresponding bit of Port 0 is defined as an I/O bit. D0-D7 - P00-P07 Mode, 0 = I/O, 1 = Address. Figure 35. Port Mode Register (pm), R241 Bank 0 Bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Initial Value X X 1 0 0 0 0 1 Read/Write ? ? ? ? ? ? ? ? The Port Mode register provides some additional mode control for Ports 0 and 1. D0 - Port 0 Direction - If this bit is a 1, all bits of Port 0 configured as I/O will be inputs. If this bit is a 0, the I/O lines will be outputs. D1 - Open-Drain Port 0 - If this bit is a 1, all bits of Port 0 configured as outputs will be open-drain outputs. If 0, they will be push-pull outputs. This bit has no effect on those bits not configured as outputs. D2 - Open-Drain Port 1 - If Port 1 is configured as an output port and this bit is a 1, all of the port will be open-drain outputs. If this bit is a 0, they will be push-pull outputs. This bit has no effect if Port 1 is not configured as an output port or A/D 0-7. D3 - Enable /DM - If this bit is a 1, Port 35 is configured as Data Memory output line /DM. D4-D5 - This field selects the configuration of Port 1 as an output port, input port, or address/data port as part of the external memory interface. Figure 36. Handshake 0 Control (H0C), R244 Bank 0 Bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Initial Value X X X X X 0 X 0 Read/Write W/O W/O W/O W/O W/O W/O W/O W/O This register controls Handshake Channel 0. |
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