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MPC8541ECVTALF 数据表(PDF) 46 Page - Freescale Semiconductor, Inc |
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MPC8541ECVTALF 数据表(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 84 page  MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4 46 Freescale Semiconductor JTAG 11 JTAG This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8541E. Table 38 provides the JTAG AC timing specifications as defined in Figure 31 through Figure 34. High period of SCL tSCHCL 4- μs Start condition setup time tSCHDL 2- μs Start condition hold time tSDLCL 3- μs Data hold time tSCLDX 2- μs Data setup time tSDVCH 3- μs SDA/SCL rise time tSRISE -1 μs SDA/SCL fall time (master) tSFALL - 303 ns Stop condition setup time tSCHDH 2- μs Table 37. CPM I2C Timing (fSCL=400KHz) Characteristic Expression Frequency = 400KHz Unit Min Max SCL clock frequency (slave) fSCL 400 KHz SCL clock frequency (master) fSCL -400 KHz Bus free time between transmissions tSDHDL 1.2 - μs Low period of SCL tSCLCH 1.2 - μs High period of SCL tSCHCL 1- μs Start condition setup time tSCHDL 420 - ns Start condition hold time tSDLCL 630 - ns Data hold time tSCLDX 420 - ns Data setup time tSDVCH 630 - ns SDA/SCL rise time tSRISE - 250 ns SDA/SCL fall time tSFALL -75 ns Stop condition setup time tSCHDH 420 - ns Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions (see Table 2). Parameter Symbol 2 Min Max Unit Notes JTAG external clock frequency of operation fJTG 0 33.3 MHz JTAG external clock cycle time t JTG 30 — ns JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns JTAG external clock rise and fall times tJTGR & tJTGF 02 ns TRST assert time tTRST 25 — ns 3 Table 36. CPM I2C Timing (fSCL=100KHz) (continued) Characteristic Expression Frequency = 100KHz Unit Min Max |
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