MPC8541ECVTALF datasheet(76/84 Pages) FREESCALE

76 / 84 page

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

System Design Information

Figure 48 shows the PLL power supply filter circuit.

Figure 48. PLL Power Supply Filter Circuit

17.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the MPC8541E can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8541E system, and the

MPC8541E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that

the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins

of the MPC8541E. These decoupling capacitors should receive their power from separate VDD, OVDD,

GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.

Capacitors may be placed directly under the device using a standard escape pattern. Others may surround

the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip

capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the

quick response time necessary. They should also be connected to the power and ground planes through two

vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo

OSCON).

17.4

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high

inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of

the MPC8541E.

17.5

Output Buffer DC Impedance

The MPC8541E drivers are characterized over process, voltage, and temperature. For all buses, the driver

is a push-pull single-ended driver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD

or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 49). The

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

VDD

AVDD (or L2AVDD)

2.2 µF

GND

Low ESL Surface Mount Capacitors

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