MPC8541ECVTALF datasheet(17/84 Pages) FREESCALE

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR SDRAM

MCS(n) output hold with respect to MCK

333 MHz

266 MHz

200 MHz

tDDKHCX

2.0

2.65

3.8

—ns

MCK to MDQS

333 MHz

266 MHz

200 MHz

tDDKHMH

-0.9

-1.1

-1.2

0.3

0.5

0.6

MDQ/MECC/MDM output setup with respect to

MDQS

333 MHz

266 MHz

200 MHz

tDDKHDS,

tDDKLDS

900

1200

—ps

MDQ/MECC/MDM output hold with respect to

MDQS

333 MHz

266 MHz

200 MHz

tDDKHDX,

tDDKLDX

900

1200

—ps

MDQS preamble start

tDDKHMP

-0.5

× t

MCK – 0.9

-0.5

× t

MCK +0.3

MDQS epilogue end

tDDKLME

-0.9

0.3

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until

outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock

reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control

address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks

by 1/2 applied cycle. The MCSx pins are separated from the ADDR/CMD (address and command) bus in the HW spec. This

was separated because the MCSx pins typically have different loadings than the rest of the address and command bus,

even though they have the same timings.

5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing

(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). In the source synchronous mode,

MDQS can launch later than MCK by 0.3 ns at the maximum. However, MCK may launch later than MDQS by as much as

0.9 ns. tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source

synchronous mode, this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing

parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the

MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description and

understanding of the timing modifications enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8541E.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8541E. Note that tDDKHMP follows the symbol

conventions described in note 1.

Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)

At recommended operating conditions with GVDD of 2.5 V ± 5%.

Parameter

Symbol 1

Min

Max

Unit

Notes

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