PIC18F258-ESLASHSOSQTP datasheet(109/402 Pages) MICROCHIP

109 / 402 page

DS41159E-page 107

PIC18FXX8

10.0

PARALLEL SLAVE PORT

In addition to its function as a general I/O port, PORTD

can also operate as an 8-bit wide Parallel Slave Port

(PSP) or microprocessor port. PSP operation is

controlled by the 4 upper bits of the TRISE register

(Register 9-1).

Setting

control

bit

PSPMODE

(TRISE<4>) enables PSP operation. In Slave mode,

the port is asynchronously readable and writable by the

external world.

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the PORTD latch as an 8-bit latch. Setting

the control bit PSPMODE enables the PORTE I/O pins

to become control inputs for the microprocessor port.

When set, port pin RE0 is the RD input, RE1 is the WR

input and RE2 is the CS (chip select) input. For this

functionality, the corresponding data direction bits of

the TRISE register (TRISE<2:0>) must be configured

as inputs (set).

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

The timing for the control signals in Write and Read

modes is shown in Figure 10-2 and Figure 10-3,

respectively.

FIGURE 10-1:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

FIGURE 10-2:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Note:

The Parallel Slave Port is only available on

PIC18F4X8 devices.

Data Bus

WR LATD

RDx pin

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

TTL

WR PORTD

RD LATD

Data Latch

Note:

I/O pins have diode protection to VDD and VSS.

PORTE pins

IBF

OBF

PSPIF

PORTD

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