PIC18F258-ESLASHSOSQTP datasheet(117/402 Pages) MICROCHIP

117 / 402 page

DS41159E-page 115

PIC18FXX8

12.2

Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON register). The

oscillator is a low-power oscillator rated up to 50 kHz. It

will continue to run during Sleep. It is primarily intended

for a 32 kHz crystal. Table 12-1 shows the capacitor

selection for the Timer1 oscillator.

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

12.3

Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The TMR1

Interrupt, if enabled, is generated on overflow which is

latched in interrupt flag bit, TMR1IF (PIR registers). This

interrupt can be enabled/disabled by setting/clearing

TMR1 Interrupt Enable bit, TMR1IE (PIE registers).

12.4

Resetting Timer1 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode

generate

“special

event

trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer1 and start an A/D conversion (if the A/D module

is enabled).

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a special

event trigger from CCP1, the write will take precedence.

In this mode of operation, the CCPR1H:CCPR1L register

pair effectively becomes the period register for Timer1.

12.5

Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit (T1CON

buffer register for the high byte of Timer1. A read from

TMR1L will load the contents of the high byte of Timer1

into the Timer1 High Byte Buffer register. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, is valid

due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

TABLE 12-1:

CAPACITOR SELECTION FOR

THE ALTERNATE

OSCILLATOR

Osc Type

Freq

32 kHz

TBD(1)

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A

±20 PPM

Note 1: Microchip suggests 33 pF as a starting

point in validating the oscillator circuit.

2: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external components.

4: Capacitor values are for design guidance

only.

Note:

The special event triggers from the CCP1

module will not set interrupt flag bit,

TMR1IF (PIR registers).

PIC18F258-E/SOSQTP 数据表(PDF) 117 Page - Microchip Technology

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