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PIC18F258-E/SOSQTP 数据表(PDF) 135 Page - Microchip Technology |
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PIC18F258-E/SOSQTP 数据表(HTML) 135 Page - Microchip Technology |
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135 / 402 page  © 2006 Microchip Technology Inc. DS41159E-page 133 PIC18FXX8 16.2 Capture Mode The Capture mode of the ECCP module is virtually identical in operation to that of the standard CCP mod- ule as discussed in Section 15.1 “CCP1 Module”. The differences are in the registers and port pins involved: • The 16-bit Capture register is ECCPR1 (ECCPR1H and ECCPR1L); • The capture event is selected by control bits ECCP1M3:ECCP1M0 (ECCP1CON<3:0>); • The interrupt bits are ECCP1IE (PIE2<0>) and ECCP1IF (PIR2<0>); and • The capture input pin is RD4 and its corresponding direction control bit is TRISD<4>. Other operational details, including timer selection, output pin configuration and software interrupts, are exactly the same as the standard CCP module. 16.2.1 CAN MESSAGE TIME-STAMP The special capture event for the reception of CAN mes- sages (Section 15.2.5 “CAN Message Time-Stamp”) is not available with the ECCP module. 16.3 Compare Mode The Compare mode of the ECCP module is virtually identical in operation to that of the standard CCP module as discussed in Section 15.2 “Capture Mode”. The differences are in the registers and port pins as described in Section 16.2 “Capture Mode”. All other details are exactly the same. 16.3.1 SPECIAL EVENT TRIGGER Except as noted below, the special event trigger output of ECCP1 functions identically to that of the standard CCP module. It may be used to start an A/D conversion if the A/D module is enabled. TABLE 16-4: REGISTERS ASSOCIATED WITH ENHANCED CAPTURE, COMPARE, TIMER1 AND TIMER3 Note: The special event trigger from the ECCP1 module will not set the Timer1 or Timer3 interrupt flag bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP -1-1 1111 -1-1 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 ECCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu ECCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module and Timer1. |
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