PIC18F258-ESLASHSOSQTP datasheet(138/402 Pages) MICROCHIP

138 / 402 page

PIC18FXX8

DS41159E-page 136

16.5.2

HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as

outputs to drive push-pull loads. The RD4/PSP4/

ECCP1/P1A pin has the PWM output signal, while the

RD5/PSP5/P1B pin has the complementary PWM

output signal (Figure 16-3). This mode can be used for

half-bridge applications, as shown in Figure 16-4, or for

full-bridge applications where four power switches are

being modulated with two PWM signals.

In Half-Bridge Output mode, the programmable dead-

band delay can be used to prevent shoot-through

current in bridge power devices. The value of register

ECCP1DEL dictates the number of clock cycles before

the output is driven active. If the value is greater than

the duty cycle, the corresponding output remains

inactive during the entire cycle. See Section 16.5.4

“Programmable Dead-Band Delay” for more details

of the dead-band delay operations.

Since the P1A and P1B outputs are multiplexed with

the PORTD<4> and PORTD<5> data latches, the

TRISD<4> and TRISD<5> bits must be cleared to

configure P1A and P1B as outputs.

FIGURE 16-3:

HALF-BRIDGE PWM

OUTPUT

FIGURE 16-4:

EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

Period

Duty Cycle

(1)

P1A(2)

P1B(2)

td = Dead-Band Delay

Period

(1)

Note

1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as asserted high.

PIC18F448/458

P1A

P1B

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

PIC18F448/458

P1A

P1B

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

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