PIC18F258-ESLASHSOSQTP datasheet(149/402 Pages) MICROCHIP

149 / 402 page

DS41159E-page 147

PIC18FXX8

17.3.3

ENABLING SPI I/O

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reinitialize the SSPCON

registers and then, set the SSPEN bit. This configures

the SDI, SDO, SCK and SS pins as serial port pins. For

the pins to behave as the serial port function, some must

have their data direction bits (in the TRIS register)

appropriately programmed as follows:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• SCK (Slave mode) must have TRISC<3> bit set

•SS must have TRISA<5> bit set

Any serial port function that is not desired may be over-

ridden

programming the corresponding data

direction (TRIS) register to the opposite value.

17.3.4

TYPICAL CONNECTION

Figure 17-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their

programmed clock edge and latched on the opposite

edge of the clock. Both processors should be

programmed to the same Clock Polarity (CKP), then

both controllers would send and receive data at the

same time. Whether the data is meaningful (or dummy

data) depends on the application software. This leads

to three scenarios for data transmission:

• Master sends data – Slave sends dummy data

• Master sends data – Slave sends data

• Master sends dummy data – Slave sends data

FIGURE 17-2:

SPI™ MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI™ Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI™ Slave SSPM3:SSPM0 = 010xb

Serial Clock

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