8.2.1 Design Requirements

For this design example, use the parameters provided in Table 8-1.

Table 8-1. Design Parameters

PARAMETER(1)

VALUE

Redriver to USB3 Hub maximum PCB trace length, XAB

8 inches

Redriver to DP RX maximum PCB trace length, XEF

6 inches

Redriver to Type-C connector maximum PCB trace length, XCD

2 inches

Maximum distance of ESD component from the USB receptacle, LESD

1.0 inches

Maximum distance of series resistor (RESD) from ESD component, LR_ESD.

0.25 inches

CAC-USB1 AC-coupling capacitor (75nF to 265nF)

100nF or 220nF

CAC-USB2 AC-coupling capacitor (297nF to 363nF)

Options:

•

RX1 and RX2 are DC-coupled to USB receptacle

•

330nF AC-couple with RRX resistor

Optional RRX resistor (220kΩ ± 5%)

220kΩ ± 5%

Optional RESD (0Ω to 2.2Ω)

1Ω

VCC supply (3V to 3.6V)

3.3V

I2C Mode or GPIO Mode

I2C Mode. (I2C_EN pin != "0")

1.8V or 3.3V I2C Interface

3.3V I2C. Pullup the I2C_EN pin to 3.3V with a 1K ohm resistor. CTL1, EQ[1:0],

SSEQ[1:0], and DPEQ[1:0] pin unconnected.

EQ setting for DisplayPort Lanes

EQ Setting # 5 (Register 0x0A[4] = 1'b1, 0x10 = 0x55; 0x11 = 0x55)

EQ setting for Downstream USB Data Path

EQ Setting # 6 (Register 0x0A[4] = 1'b1, 0x20 = 0x66)

EQ setting for Upstream USB Data Path

EQ Setting # 6 (Register 0x0A[4] = 1'b1, 0x21 = 0x08)

(1)

Maximum trace length assumes an insertion loss of 0.2dB/inch/GHz. If insertion loss is more than 0.2dB/inch/GHz, then maximum

trace length must be reduced accordingly.

8.2.2 Detailed Design Procedure

A typical usage of the TUSB564-Q1 device is shown in Figure 8-2. The device can be controlled either

through its GPIO pins or through its I2C interface. In the example shown below, a Type-C PD controller is

used to configure the device through the I2C interface. In I2C mode, the equalization settings for each receiver

can be independently controlled through I2C registers. For this reason, the configuration pin CTL1 and all

of the equalization pins (EQ[1:0], SSEQ[1:0], and DPEQ[1:0]) can be left unconnected. If these pins are left

unconnected, the TUSB564-Q1 7-bit I2C target address is 0x12 because both DPEQ/A1 and SSEQ0/A0 are at

pin level "F". If a different I2C target address is desired, set the DPEQ/A1 and SSEQ0/A0 pins to a level which

produces the desired I2C target address.

TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

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