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TUSB564 数据表(PDF) 22 Page - Texas Instruments |
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TUSB564 数据表(HTML) 22 Page - Texas Instruments |
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22 / 52 page ![]() 7.4.2 Device Configuration In I2C Mode The TUSB564-Q1 is in I2C mode when I2C_EN is not equal to 0. The same configurations defined in GPIO mode are also available in I2C mode. The TUSB564-Q1 USB and DisplayPort configuration is controlled based on Table 7-5. The AUXp or AUXn to SBU1 or SBU2 mapping control is based on Table 7-6. Table 7-5. I2C Configuration Control REGISTERS CONFIGURATION VESA DisplayPort ALT MODE UFP_D CONFIGURATION CTLSEL1 CTLSEL0 FLIPSEL 0 0 0 Power Down — 0 0 1 Power Down — 0 1 0 One Port USB – No Flip — 0 1 1 One Port USB – With Flip — 1 0 0 4 Lane DP – No Flip C 1 0 1 4 Lane DP – With Flip C 1 1 0 One Port USB + 2 Lane DP – No Flip D 1 1 1 One Port USB– + 2 Lane DP – With Flip D Table 7-6. I2C AUXp or AUXn to SBU1 or SBU2 Mapping REGISTERS MAPPING AUX_SBU_OVR CTLSEL1 FLIPSEL 00 1 0 SBU1 → AUXn SBU2 → AUXp 00 1 1 SBU2 → AUXn SBU1 → AUXp 00 0 X Open 01 X X SBU1 → AUXn SBU2 → AUXp 10 X X SBU2 → AUXn SBU1 → AUXp 11 X X Open 7.4.3 DisplayPort Mode The TUSB564-Q1 supports up to four DisplayPort lanes at datarates up to 8.1Gbps. The TUSB564-Q1 can be enabled for DisplayPort through the GPIO control pin CTL1 or through the I2C register CTLSEL1. When I2C_EN is "0", DisplayPort is controlled based on Table 7-2. When not in GPIO mode, DisplayPort functionality is controlled through I2C registers. Data transfer through the DisplayPort lanes is further controlled by the HPDIN pin. DisplayPort must be enabled using CTL1 pin or CTLSEL1 register and also HPDIN must be pulled high for the DisplayPort data transfer to be enabled through the DisplayPort lanes. Note When operating in 4-lane DP mode (CTLSEL[1:0] = 2h) with AUX snoop disabled (AUX_SNOOP_DISABLE = 1), all four DP lanes must be enabled (DP0_DISABLE = DP1_DISABLE = DP2_DISABLE = DP3_DISABLE = "0"). With AUX snoop disabled (AUX_SNOOP_DISABLE = 1) and CTLESEL[1:0] = 2h, the individual DP lane disable/enable for DP0 and DP3 are swapped and DP1 and DP2 are swapped. DP0_DISABLE controls DP3, DP3_DISABLE controls DP0, DP1_DISABLE controls DP2, and DP2_DISABLE controls DP1. TUSB564-Q1 SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024 www.ti.com 22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB564-Q1 |
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