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TUSB564 数据表(PDF) 11 Page - Texas Instruments |
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TUSB564 数据表(HTML) 11 Page - Texas Instruments |
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11 / 52 page ![]() 5.7 Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TGP_USB_ 4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa 4 µs THPDIN_D EBOUNCE HPDIN debounce time when transitioning from H to L Less than minimum is ignored by device 1.5 4 ms I2C (SDA and SCL) fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0.004 µs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Device output fall time for SDA 30pF load 0.7 5 ns tSUSTO Setup time for STOP condition 0.26 µs Cb Capacitive load for each bus line 100 pF www.ti.com TUSB564-Q1 SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TUSB564-Q1 |
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