TUSB564 datasheet(27/52 Pages) TI

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Target Address

Write

Ack

Start

Repeated Start

Target Address

Data from Register Xh

Read

Stop

Data from Register Xh + 1

Figure 7-4. I2C Read with Repeated Start

Use the following procedure to read the TUSB564-Q1 I2C registers with a repeated Start (refer Figure 7-4).

1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB564-Q1

7-bit address and a zero-value W/R bit to indicate a write cycle.

2. The TUSB564-Q1 acknowledges the 7-bit address cycle.

3. The controller presents the register offset within TUSB564-Q1 to be written, consisting of one byte of data,

MSB-first.

4. The TUSB564-Q1 acknowledges the register offset cycle.

5. The controller presents a repeated start condition (Sr).

6. The controller initiates a read operation by generating a start condition (S), followed by the TUSB564-Q1

7-bit address and a one-value W/R bit to indicate a read cycle.

7. The TUSB564-Q1 acknowledges the 7-bit address cycle.

8. The TUSB564-Q1 transmit the contents of the memory registers MSB-first starting at the register offset.

9. The TUSB564-Q1 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the

controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.

10. If an ACK is received, the TUSB564-Q1 transmits the next byte of data as long as controller provides the

clock. If a NAK is received, the TUSB564-Q1 stops providing data and waits for a stop condition (P).

11. The controller terminates the read operation by generating a stop condition (P).

Target Address

Write

Ack

Start

Stop

Figure 7-5. I2C Write Without Data

Use the following procedure to set a starting sub-address for I2C reads (refer to Figure 7-5).

1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB564-Q1

7-bit address and a zero-value W/R bit to indicate a write cycle.

2. The TUSB564-Q1 acknowledges the address cycle.

3. The controller presents the register offset within TUSB564-Q1 to be written, consisting of one byte of data,

MSB-first.

4. The TUSB564-Q1 acknowledges the register offset cycle.

5. The controller terminates the write operation by generating a stop condition (P).

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TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

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