TUSB564 datasheet(20/52 Pages) TI

20 / 52 page

Note

All 4-level inputs are latched after the rising edge of internal reset. After tcfg_hd, the internal pullup and

pulldown resistors are isolated to save power.

7.3.4 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and the resulting inter-symbol

interference in the system before the input or after the output of the TUSB564-Q1. The receiver overcomes

these losses by attenuating the low-frequency components of the signals with respect to the high-frequency

components. Select the proper gain setting to match the channel insertion loss. Two 4-level input pins enable

up to 16 possible equalization settings. The USB3.2 upstream path, USB3.2 downstream path, and DisplayPort

each have two 4-level inputs. The TUSB564-Q1 also provides the flexibility of adjusting settings through I2C

registers.

7.4 Device Functional Modes

7.4.1 Device Configuration in GPIO Mode

The TUSB564-Q1 is in GPIO configuration when I2C_EN = "0". The TUSB564-Q1 supports the following

configurations: USB only, 2 DisplayPort lanes + USB, or 4 DisplayPort lanes (no USB). The CTL1 pin controls

whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB only, 2 lanes of

DisplayPort, or 4-lanes of DisplayPort as detailed in Table 7-2. The AUXp or AUXn to SBU1 or SBU2 mapping is

controlled based on Table 7-3.

After power up (VCC from 0V to 3.3V), the TUSB564-Q1 defaults to USB mode. The USB PD controller upon

detecting no device attached to Type-C port must take TUSB564-Q1 out of USB mode by transitioning the CTL0

pin from L to H and back to L.

Table 7-2. GPIO Configuration Control

CTL1 PIN

CTL0 PIN

FLIP PIN

CONFIGURATION

VESA DisplayPort ALT MODE

UFP_D CONFIGURATION

Power Down

—

Power Down

—

One Port USB – No Flip

—

One Port USB – With Flip

—

4 Lane DP – No Flip

4 Lane DP – With Flip

One Port USB + 2 Lane DP – No Flip

One Port USB + 2 Lane DP – With Flip

Table 7-3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping

CTL1 PIN

FLIP PIN

MAPPING

SBU1 → AUXn

SBU2 → AUXp

SBU2 → AUXn

SBU1 → AUXp

L > 2ms

Open

Table 7-4 details the TUSB564-Q1 MUX routing. This table is valid for both I2C and GPIO configuration modes.

TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

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