TUSB564 datasheet(40/52 Pages) TI

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9 Register Maps

Table 9-1. Register Legend

ACCESS TAG

NAME

MEANING

Read

The field can be read by software

Write

The field can be written by software

Set

The field can be set by a write of one. Writes of zeros to the field have no effect.

Clear

The field can be cleared by a write of one. Write of zero to the field have no effect.

Update

Hardware can autonomously update this field.

No Access

Not accessible or not applicable

9.1 General Register (address = 0x0A) [reset = 00000001]

Figure 9-1. General Registers

Reserved

EQ_OVERRIDE HPDIN_OVRRI

FLIPSEL

CTLSEL[1:0].

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-2. General Registers

Bit

Field

Type

Reset

Description

7:5

Reserved.

EQ_OVERRIDE

R/W

Setting this field allows software to use EQ settings from

registers instead of value sample from pins.

0: EQ settings based on sampled state of the EQ pins

(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).

1: EQ settings based on programmed value of each of the EQ

registers

DP_EN_CTRL

R/W

Controls whether DisplayPort functionality is controlled by

CTLSEL1 register or CTL1 pin.

0: DisplayPort enable/disable is based on CTLSEL1 register.

1: DisplayPort enable/disable is based on state of CTL1 pin.

FLIPSEL

R/W

FLIPSEL. Refer to Table 7-5 and Table 7-6 for this field

functionality.

1:0

CTLSEL[1:0].

R/W

00: Disabled. All RX and TX for USB3 and DisplayPort are

disabled.

01: USB3.1 only enabled. (Default)

10: Four DisplayPort lanes enabled.

11: Two DisplayPort lanes and one USB3.1

9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]

Figure 9-2. DisplayPort Control/Status Registers (0x10)

DP1EQ_SEL

DP3EQ_SEL

R/W/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-3. DisplayPort Control/Status Registers (0x10)

Bit

Field

Type

Reset

Description

7:4

DP1EQ_SEL

R/W/U

0000

Field selects EQ level for DP lane 1. When EQ_OVERRIDE =

1’b0, this field reflects the sampled state of DPEQ[1:0] pins.

When EQ_OVERRIDE = 1’b1, software can change the EQ

setting for DP lane 1 based on value written to this field.

TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

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