数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

TUSB564 数据表(PDF) 23 Page - Texas Instruments

Click here to check the latest version.
部件名 TUSB564
功能描述  TUSB564-Q1 Automotive USB Type-C® DP Alt Mode 8.1Gbps Sink-Side Linear Redriver Crosspoint Switch
PDF  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TUSB564 数据表(HTML) 23 Page - Texas Instruments

Back Button TUSB564 Datasheet HTML 19Page - Texas Instruments TUSB564 Datasheet HTML 20Page - Texas Instruments TUSB564 Datasheet HTML 21Page - Texas Instruments TUSB564 Datasheet HTML 22Page - Texas Instruments TUSB564 Datasheet HTML 23Page - Texas Instruments TUSB564 Datasheet HTML 24Page - Texas Instruments TUSB564 Datasheet HTML 25Page - Texas Instruments TUSB564 Datasheet HTML 26Page - Texas Instruments TUSB564 Datasheet HTML 27Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 52 page
background image
7.4.4 Linear EQ Configuration
Each of the TUSB564-Q1 receiver lanes has individual controls for receiver equalization. The receiver
equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7-7 details the
gain value for each available combination when TUSB564-Q1 is in GPIO mode. These same options are also
available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL,
EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as
follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit
values as: 0 = 00, R = 01, F = 10, 1 = 11.
Table 7-7. TUSB564-Q1 Receiver Equalization GPIO Control
EQUALIZATION
SETTING #
USB3.1 UPSTREAM FACING PORTS
USB 3.1 DOWNSTREAM FACING PORT
ALL DISPLAYPORT LANES
EQ1 PIN LEVEL
EQ0 PIN LEVEL
EQ GAIN AT
2.5GHz (dB)
SSEQ1 PIN
LEVEL
SSEQ0 PIN
LEVEL
EQ GAIN AT
2.5GHz (dB)
DPEQ1 PIN
LEVEL
DPEQ0 PIN
LEVEL
EQ GAIN AT
4.05GHz (dB)
0
0
0
–0.7
0
0
-0.9
0
0
1.0
1
0
R
1.8
0
R
0.2
0
R
3.0
2
0
F
2.7
0
F
1.1
0
F
4.4
3
0
1
3.7
0
1
2.2
0
1
5.8
4
R
0
4.6
R
0
3.0
R
0
6.8
5
R
R
5.5
R
R
4.0
R
R
8.0
6
R
F
6.3
R
F
4.8
R
F
8.8
7
R
1
7.0
R
1
5.6
R
1
9.6
8
F
0
7.8
F
0
6.4
F
0
10.4
9
F
R
8.5
F
R
7.0
F
R
11.0
10
F
F
9.1
F
F
7.6
F
F
11.6
11
F
1
9.7
F
1
8.2
F
1
12.1
12
1
0
10.1
1
0
8.7
1
0
12.5
13
1
R
10.7
1
R
9.2
1
R
13.0
14
1
F
11.1
1
F
9.7
1
F
13.4
15
1
1
11.6
1
1
10.2
1
1
13.7
7.4.5 USB3 Modes
The TUSB564-Q1 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.2 interface, the TUSB564-Q1 can be in one of four primary modes of operation when USB 3.2 is enabled
(CTL0 = H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB564-Q1 has not detected far-end termination on upstream
facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of
the four modes. The TUSB564-Q1 remains in this mode until far-end receiver termination has been detected on
both UFP and DFP. The TUSB564-Q1 immediately exits this mode and enters U0 after far-end termination is
detected.
When in U0 mode, the TUSB564-Q1 redrives all traffic received on UFP and DFP. U0 is the highest power mode
of all USB3.1 modes. The TUSB564-Q1 remains in U0 mode until electrical idle occurs on both UFP and DFP.
Upon detecting electrical idle, the TUSB564-Q1 immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB564-Q1 UFP
and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB564-Q1
periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB564-Q1 leaves the U2/U3 mode and transitions to the Disconnect mode. The
device also monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB564-Q1 immediately transitions
to the U0 mode. In U2/U3 mode, the TUSB564-Q1 receiver terminations remain enabled but the TX DC common
mode voltage is not maintained.
www.ti.com
TUSB564-Q1
SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TUSB564-Q1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com