TUSB564 datasheet(26/52 Pages) TI

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7.5.1 TUSB564-Q1 I2C Target Behavior

Target Address

Write

Ack

Start

Data wri en

Figure 7-2. I2C Write with Data

Use the following procedure to write data to TUSB564-Q1 I2C registers (refer to Figure 7-2):

1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB564-Q1

7-bit address and a zero-value W/R bit to indicate a write cycle.

2. The TUSB564-Q1 acknowledges the address cycle.

3. The controller presents the register offset within TUSB564-Q1 to be written, consisting of one byte of data,

MSB-first.

4. The TUSB564-Q1 acknowledges the sub-address cycle.

5. The controller presents the first byte of data to be written to the I2C register.

6. The TUSB564-Q1 acknowledges the byte transfer.

7. The controller can continue presenting additional bytes of data to be written, with each byte transfer

completing with an acknowledge from the TUSB564-Q1.

8. The controller terminates the write operation by generating a stop condition (P).

Target Address

Data from o set 0x00

last read address + 1

Read

Ack

Start

Stop

Figure 7-3. I2C Read Without Repeated Start

Use the following procedure to read the TUSB564-Q1 I2C registers without a repeated Start (refer Figure 7-3).

1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB564-Q1

7-bit address and a zero-value W/R bit to indicate a read cycle.

2. The TUSB564-Q1 acknowledges the 7-bit address cycle.

3. Following the acknowledge the controller continues sending clock.

4. The TUSB564-Q1 transmit the contents of the memory registers MSB-first starting at register 00h or last

read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB564-Q1 shall

start at the register offset specified in the write.

5. The TUSB564-Q1 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller

after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.

6. If an ACK is received, the TUSB564-Q1 transmits the next byte of data as long as controller provides the

clock. If a NAK is received, the TUSB564-Q1 stops providing data and waits for a stop condition (P).

7. The controller terminates the write operation by generating a stop condition (P).

TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

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