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ST7LITEUSX 数据表(PDF) 22 Page - STMicroelectronics

部件名 ST7LITEUSX
功能描述  8-bit MCU with single voltage Flash memory, ADC, timers
PDF  108 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITEUSX 数据表(HTML) 22 Page - STMicroelectronics

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6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 12:
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to Figure 12.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 11:
Active Phase depending on the RESET source
64 CPU clock cycle delay
RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
The 64 CPU clock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
Figure 12. Reset Block Diagram
RESET
Active Phase
INTERNAL RESET
64 CLOCK CYCLES
FETCH
VECTOR
RESET
RON
VDD
INTERNAL
RESET
PULSE
GENERATOR
FILTER
LVD RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
Note 1: See “Illegal Opcode Reset” on page 64. for more details on illegal opcode reset conditions.
1



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