ST7LITEUSX datasheet(35/108 Pages) STMICROELECTRONICS

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ST7LITEUSx

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POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the LTCSR/ATCSR reg-

ister status as shown in the following table:.

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when active halt mode is enabled.

The MCU can exit ACTIVE-HALT mode on recep-

tion of a Lite Timer / AT Timer interrupt or a RE-

SET.

– When exiting ACTIVE-HALT mode by means of

a RESET, a 64 CPU cycle delay occurs. After the

start up delay, the CPU resumes operation by

fetching the reset vector which woke it up (see

Figure 22).

– When exiting ACTIVE-HALT mode by means of

an interrupt, the CPU immediately resumes oper-

ation by servicing the interrupt vector which woke

it up (see Figure 22).

When entering ACTIVE-HALT mode, the I bit in

the CC register is cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator

and the selected timer counter (LT/AT) are running

to keep a wake-up time base. All other peripherals

are not clocked except those which get their clock

supply from another clock generator (such as ex-

ternal or auxiliary oscillator).

Caution: As soon as ACTIVE-HALT is enabled,

executing a HALT instruction while the Watchdog

is active does not generate a RESET if the

WDGHALT bit is reset.

This means that the device cannot spend more

than a defined delay in this power saving mode.

Figure 21. ACTIVE-HALT Timing Overview

Figure 22. ACTIVE-HALT Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripherals clocked with an external clock

source can still be active.

3. Only the Lite Timer RTC and AT Timer interrupts

can exit the MCU from ACTIVE-HALT mode.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

LTCSR

TBIE bit

ATCSR

OVFIE

bit

ATCSR

CK1 bit

ATCSR

CK0 bit

Meaning

ACTIVE-HALT

mode disabled

xxx

ACTIVE-HALT

mode enabled

HALT

RUN

64 CPU

CYCLE DELAY 1)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[Active Halt Enabled]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

X 4)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X 4)

64 CPU CLOCK CYCLE

DELAY

(Active Halt enabled)

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