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ST7LITEUSX 数据表(PDF) 49 Page - STMicroelectronics |
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ST7LITEUSX 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 108 page  ST7LITEUSx 49/108 LITE TIMER (Cont’d) Input Capture The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always con- tains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 10.1.4 Low Power Modes 10.1.5 Interrupts Note: The TBF and ICF interrupt events are con- nected to separate interrupt vectors (see Inter- rupts chapter). They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction). Figure 32. Input Capture Timing Diagram Mode Description WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Exit from Active- Halt Timebase Event TBF TBIE Yes No Yes IC Event ICF ICIE Yes No No 0004h 13-bit COUNTER t 0001h fOSC xxh 0002h 0003h 0005h 0006h 0007h 04h LTIC PIN ICF FLAG LTICR REGISTER CLEARED 125ns (@ 8MHz fOSC) fCPU BY S/W 07h READING LTIC REGISTER 1 |
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