VS1103B datasheet(16/61 Pages) ETC2

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VLSI

Solution

VS1103b

VS1103B

5. SPI BUSES

5.3 Data Request Pin DREQ

The DREQ pin/signal is used to signal if VS1103b’s SDI FIFO is capable of receiving data. If DREQ is

high, VS1103b can take at least 32 bytes of SDI data or one SCI command.

Because of a 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without

checking the status of DREQ, making controlling VS1103b easier for low-speed microcontrollers. If

SARC DREQ512 is set, the safety area is 512 bytes (see Chapter 6.6.13).

Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should

only be used to decide whether to send more bytes. It should not abort a transmission that has already

started.

Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1103b DREQ is also

used to tell the status of SCI.

5.4 Serial Protocol for Serial Data Interface (SDI)

5.4.1 General

The serial data interface operates in slave mode so the DCLK signal must be generated by an external

circuit.

Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 6.6).

VS1103b assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or

LSb ﬁrst, depending of SCI MODE (Chapter 6.6.1).

5.4.2 SDI in VS1002 Native Modes (Recommended)

In VS1002 native modes (SM NEWMODE is 1), byte synchronization is achieved by XDCS. The state of

XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization

even if there may be glitches in the boards using VS1103b, it is recommended to turn XDCS every now

and then, for instance once after every ﬂash data block or a few kilobytes, just to keep sure the host and

VS1103b are in sync.

If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.

For new designs, using VS1002 native modes are recommended.

Version 1.01, 2007-09-03

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