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VLSI
Solution
y
VS1103b
VS1103B
8. VS1103B REGISTERS
8.12 Timers v1.0 2002-04-23
There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled,
a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle.
When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value
register, and continues downcounting. A timer stays in that loop as long as it is enabled.
A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding the
timer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer is
enabled (1) or disabled (0) by a corresponding bit of the enable register.
8.12.1 Registers
Timer registers, prefix TIMER
Reg
Type
Reset
Abbrev
Description
0xC030
r/w
0
CONFIG[7:0]
Timer configuration
0xC031
r/w
0
ENABLE[1:0]
Timer enable
0xC034
r/w
0
T0L
Timer0 startvalue - LSBs
0xC035
r/w
0
T0H
Timer0 startvalue - MSBs
0xC036
r/w
0
T0CNTL
Timer0 counter - LSBs
0xC037
r/w
0
T0CNTH
Timer0 counter - MSBs
0xC038
r/w
0
T1L
Timer1 startvalue - LSBs
0xC039
r/w
0
T1H
Timer1 startvalue - MSBs
0xC03A
r/w
0
T1CNTL
Timer1 counter - LSBs
0xC03B
r/w
0
T1CNTH
Timer1 counter - MSBs
8.12.2 Configuration TIMER CONFIG
TIMER CONFIG Bits
Name
Bits
Description
TIMER CF CLKDIV
7:0
Master clock divider
TIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clock
frequency fi =
fm
c+1 , where fm is the master clock frequency and c is TIMER CF CLKDIV. Example:
With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/sampling
clock would thus be fi = 12MHz
3+1
= 3M Hz.
Version 1.01, 2007-09-03
54
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