VS1103B datasheet(44/61 Pages) ETC2

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VLSI

Solution

VS1103b

VS1103B

7. OPERATION

7.8.3 Memory Test

Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this

sequence, wait for 500000 clock cycles. The result can be read from the SCI register SCI IN0, and ’one’

bits are interpreted as follows:

Bit(s)

Mask

Meaning

0x8000

Test ﬁnished

14:7

Unused

0x0040

Mux test succeeded

0x0020

Good I RAM

0x0010

Good Y RAM

0x0008

Good X RAM

0x0004

Good I ROM

0x0002

Good Y ROM

0x0001

Good X ROM

0x807f

All ok

Memory tests overwrite the current contents of the RAM memories.

7.8.4 SCI Test

Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n − 48 is the register

number to test. The content of the given register is read and copied to SCI IN0. If the register to be

tested is SCI IN0, the result is copied to SCI IN1.

Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI IN0.

Version 1.01, 2007-09-03

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