VLSI
Solution
y
VS1103b
VS1103B
8. VS1103B REGISTERS
8.11.3 Data UARTx DATA
A read from UARTx DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there is
no more data to be read, the receiver data register full indicator will be cleared.
A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver
data register.
A write to UARTx DATA sets a byte for transmission. The data is taken from bits 7:0, other bits in the
written value are ignored. If the transmitter is idle, the byte is immediately moved to the transmitter shift
register, a transmit interrupt request is generated, and transmission is started. If the transmitter is busy,
the UART ST TXFULL will be set and the byte remains in the transmitter data register until the previous
byte has been sent and transmission can proceed.
8.11.4 Data High UARTx DATAH
The same as UARTx DATA, except that bits 15:8 are used.
8.11.5 Divider UARTx DIV
UARTx DIV Bits
Name
Bits
Description
UART DIV D1
15:8
Divider 1 (0..255)
UART DIV D2
7:0
Divider 2 (6..255)
The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending on the
master clock frequency to get the correct bit speed. The second divider (D2) must be from 6 to 255.
The communication speed f =
fm
(D1+1)×(D2) , where fm is the master clock frequency, and f is the
TX/RX speed in bps.
Divider values for common communication speeds at 26 MHz master clock:
Example UART Speeds, fm = 26MHz
Comm. Speed [bps]
UART DIV D1
UART DIV D2
4800
85
63
9600
42
63
14400
42
42
19200
51
26
28800
42
21
38400
25
26
57600
1
226
115200
0
226
Version 1.01, 2007-09-03
52
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