VS1103B datasheet(37/61 Pages) ETC2

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VLSI

Solution

VS1103b

VS1103B

7. OPERATION

7 Operation

7.1 Clocking

VS1103b operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock

can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface

(pins XTALI and XTALO).

7.2 Hardware Reset

When the XRESET -signal is driven low, VS1103b is reset and all the control registers and internal

states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode

doubles as a full-powerdown mode, where both digital and analog parts of VS1103b are in minimum

power consumption stage, and where clocks are stopped. Also XTALO is grounded.

After a hardware reset (or at power-up) DREQ will stay down for at least 16600 clock cycles, which

means an approximate 1.35 ms delay if VS1103b is run at 12.288 MHz. After this the user should set

SCI CLOCKF, perform a software reset, and then set other basic software registers as e.g. SCI MODE,

SCI BASS, and SCI VOL before starting decoding. See section 6.6 for details.

The internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF regis-

ter are 1.0 × . . . 4.5× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If typical values

are wanted, the Internal Clock Multiplier needs to be set to 4.0× after reset. Wait until DREQ rises, then

write a proper value to SCI CLOCKF, followed by a software reset. See section 6.6.4 for details.

After XRESET is released, a software reset operation is also performed.

7.3 Software Reset

In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register

(Chapter 6.6.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for at least 16600

clock cycles, which means an approximate 1.35 ms delay if VS1103b is run at 12.288 MHz. After DREQ

is up, you may continue playback as usual.

If GPIO0 is set to 1, Spi Boot is performed (Chapter 7.5). If GPIO0 is set to 0 and GPIO1 to 1, RT-MIDI

Mode is activated (Chapter 6.3.2).

As opposed to some earlier VS10XX products, VS1103b has been designed so that using software resets

during normal operation shouldn’t be necessary.

Version 1.01, 2007-09-03

VS1103B 数据表(PDF) 37 Page - List of Unclassifed Manufacturers